I. Field of the Invention
This invention pertains to a flip-chip Vertical Cavity Surface Emitting Laser (VCSEL) bonded to a CMOS circuit. More particularly, this invention relates to an improved flip-chip bonded VCSEL CMOS circuit having a mechanism for preventing rearwardly emitted light of the VCSEL from entering the CMOS. The present invention also pertains to a flip-chip bonded VCSEL CMOS circuit having an integrated silicon monitor detector.
II. Description of the Related Art
Optical interconnections based on VCSELs can be used to advantageously provide high bandwidth optical interconnections over fiber optical cable for data communications applications. By virtue of their ability to be produced in arrays and tested in parallel, and the relative ease in coupling the laser emissions to multi-mode fiber, VCSELs have been recognized as an efficient, low cost alternative to edge-emitting semi-conductor lasers and can accommodate data rates of 1 Gbit/s. However, VCSEL sources are typically driven electrically from separate (off-chip) drivers which significantly increase the power dissipation of the driver-VCSEL package and adversely affect the bandwidth of the link.
The efficiency and performance of VCSEL sources can be increased by flip-chip bonding VCSEL devices directly to CMOS. Based on known hybrid flip-chip bonding techniques, it is possible to create three-dimensional optoelectronic-VLSI structures, with the flip-chip bonded optical devices placed directly above the silicon CMOS circuitry.
FIG. 1 depicts a known flip-chip bonded VCSEL CMOS circuit 10. The circuit contains a VCSEL 12 which operatively emits laser light h.nu., as shown, and a CMOS device 14 that powers the VCSEL. CMOS 14 contains a p-doped semiconductor substrate 16 in which a PMOS transistor 18 and an NMOS transistor 26 are formed. Each transistor has a source region (PMOS-20, NMOS-28), a drain region (PMOS-22, NMOS-30) and a gate (PMOS-24, NMOS-32).
As is known by those having ordinary skill in the art, a first metal layer 35 forms source terminals 36 and drain terminals 37 for the PMOS and CMOS devices. Gate terminals 24 and 33 are formed on a gate oxide layer 32, and insulation layers 34, 38 insulate the gate, source and drain terminals from each other. Additional metallization layers 40, 44 provide electrical communication with the source terminals 36 and drain terminals 37, respectively. These layers are insulated by insulating layers 42, 48, to form an upper major surface 50 of the CMOS device 14. Bonding pads 46 are formed on major surface 50 and are in communication with metal layers 40, 44 and, hence, with source and drain terminals 36, 37. The bonding pads are spaced apart from each other and define a region. The bonding pads are coupled to VCSEL bonding pads (not shown) via soldering, for example, and provide electrical communication between the VCSEL and CMOS. VCSEL 12 has a p-terminal 57 and an n-terminal 58 which are mounted to the bonding pads 46, as for example soldering 52, so that the p-terminal 57 is connected to the CMOS source terminals 36 and the n-terminal 58 is connected to the CMOS drain terminals 37. An epoxy layer 59 is also provided for further securing VCSEL 12 to CMOS 14. VCSEL 12 has an upper mirror or aperture 54 through which the laser light h.nu. is emitted, and a lower mirror or aperture 56 positioned proximate the CMOS major surface 50 for generating the laser light.
A major design consideration in producing large arrays of VCSEL devices is the mirror technology used to manufacture the mirror surfaces 54 and 56 on the VCSEL. While there are several emerging mirror technologies based on EPI-layer growth or deposition, reliable production of a 100% reflecting surface (to act as one of the reflectors in the micro-cavity) is difficult. Due to the lack of complete surface reflectivity in VCSELs, light may emit from both facets of the VCSEL cavity, e.g. forwardly emitted light h.nu. through upper mirror 54 and rearwardly emitted light 51 through lower mirror 56. The pressure of rearwardly emitted light becomes particularly relevant when a dense three-dimensional structure is sought, which places the laser above or near a CMOS circuit as in the flip-chip bonded VCSEL of FIG. 1. This is because the gate terminals that control the flow of CMOS current are more likely to absorb stray photons that are emitted through lower mirror 56, thus causing degradation of CMOS operation. As the flip-chip bonded VCSEL is driven by the CMOS, degradation of CMOS operation will also degrade VCSEL performance.